This invention relates to semiconductor devices. In particular, the invention relates to a multicollector vertical pnp transistor and to a method for fabricating a vertical semiconductor device using a minimum amount of material and diffusion steps.
The need for vertical pnp transistors having electrical performance similar to that of vertical npn transistors at high frequencies and medium voltages in analog applications has been known to circuit designers for several years. Unfortunately, attempts to fabricate vertical pnp transistors have not proven totally satisfactory.
For example, the lateral pnp transistor is known to have low current capabilities, poor response at high frequencies, and large dimensions.
It has also been found possible to construct a substrate pnp transistor as shown in FIG. 1A. Although this transistor has good current and frequency characteristics, the substrate actually grounds the pnp collector. As a consequence, the substrate pnp transistor encounters limited application. In addition, substrate type pnp transistors use a low concentration material for the substrate-collector, resulting in low gain for the device.
Previously fabricated vertical collector pnp transistors also suffer from several drawbacks. One example of a vertical collector pnp transistor is shown in FIG. 1B. As shown in that example vertical collector pnp transistors have been characterized by large dimensions resulting in inefficient use of silicon. As a result, high frequency response characteristics for this device have been less than desirable. In addition deep diffusion of an n well below the p collector is required to isolate the p collector from the p substrate. Moreover, fabrication of the vertical collector pnp transistor requires at least three diffusion steps. Which are costly and time-consuming processes.
A paper by Davis and Moyer, Bell Labs, Int. Electron Devices Mtg, Washington D.C., Dec. 4-6, 1972 teaches a process for making a vertical collector pnp transistor involVing the use of two epitaxial layers. FIG. 1C illustrates this device. A single vertical collector is formed in two epitaxial layers and is isolated from the p substrate by a diffused buried region. However, the technique taught by Davis and Moyer requires a minimum of four diffusion steps to form a one collector device and was not adapted for forming multicollector devices or vertical devices having a plurality of vertical conductive regions. Moreover, because the device uses a highly doped n+ base formed in a high concentration p+ collector, the transistor has a low collector to base breakdown voltage.
The only other uses of multiple epitaxial layers in connection with transistor devices known to applicant have been limited to forming isolation regions for multidevice systems.
Thus, what is needed is a vertical pnp structure and a method for fabricating a vertical pnp structure that will meet the heretofore unmet needs of the prior art. In particular, what is needed is a method of fabrication that results in a multicollector vertical pnp transistor that exhibits good gain at high current levels, has a good high frequency response and has a smaller size relative to prior art devices. A high breakdown voltage is also a desirable objective. Fabrication steps for such a device should reduce wasted materials and require a minimum number of diffusion steps.